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PM6685
DUAL STEP-DOWN CONTROLLER WITH AUXILARY VOLTAGES FOR NOTEBOOK SYSTEM POWER
Preliminary Data
Features
CONSTANT ON TIME TOPOLOGY ALLOWS VERY FAST LOAD TRANSIENTS 6V TO 28V INPUT VOLTAGE RANGE FIXED 5V-3.3V OUTPUT VOLTAGES 5V AND 3.3V ALWAYS VOLTAGES AVAILABLE DELIVER 100mA PEAK CURRENT 1.23V 1% REFERENCE VOLTAGE AVAILABLE NO RSENSE CURRENT SENSING USING LOW SIDE MOSFETs' RDS(on) ACCURATE CURRENT SENSE WITH RSENSE NEGATIVE CURRENT LIMIT SOFT START INTERNALLY FIXED AT 2ms SOFT OFF FOR OUTPUT DISCHARGE LATCHED OVP AND UVP SELECTABLE PULSE SKIPPING AT LIGHT LOADS SELECTABLE MINIMUM FREQUECY (25kHz) IN PULSE SKIP MODE 4 mW MAXIMUM QUIESCENT POWER INDIPENDENT POWER GOOD SIGNALs OUTPUT VOLTAGE RIPPLE COMPENSATION VFQFPN-32 5X5

Description
PM6685 is a dual step-down controller specifically designed to provide extremely high efficiency conversion, with lossless current sensing technique. The constant on-time architecture assures fast load transient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. An embedded integrator control loop compensates the DC voltage error due to the output ripple. Pulse skipping technique increases efficiency at very light load. Moreover a minimum switching frequency of 25kHz is selectable to avoid audio noise issues. The PM6685 provides a selectable switching frequency, allowing either 200kHz/ 300kHz, 300kHz/400Khz or 400kHz/500kHz operation of the 5V/3.3V switching sections...

Applications

NOTEBOOK COMPUTERS TABLET PC OR SLATES MOBILE SYSTEM POWER SUPPLY 3-4 CELLS Li+ BATTERY POWERED DEVICES
Order codes
Part number PM6685 September 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Marking PM6685
Package VFQFPN-32 5X5
Packing TAPE & REEL Rev 1 1/16
www.st.com 16
PM6685
Contents
1 2 3 4 5 6 7 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block & pin connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional & block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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PM6685
1 Typical application circuit
1
Figure 1.
Typical application circuit
Circuit
3/16
2 Electrical ratings
PM6685
2
Table 1.
Electrical ratings
Absolute maximum ratings
Parameter SGND1 to SGND2 COMPx, FSEL, LDO3_SEL, VREF, SKIP to SGND1, SGND2 Enx, SHDN, PGOD_LDO3, OUTx, PGOODx, V CC to SGND1, SGND2 LDO3 to SGND1, SGND2 LGATEx to PGND HGATEx and BOOTx, to PHASEx PHASEx to PGND CSENSEx, to PGND CSENSEx to BOOTx V5SW, LDO5 to PGND VIN to PGND PGND to SGND1, SGND2 Power dissipation at Tamb = 25C Value Shorted -0.3 to V CC + 0.3 -0.3 to 6 -0.3 to LDO5 + 0.3 -0.3 to LDO5 + 0.3 -0.3 to 6 -0.6 to 36 -0.6 to 42 -6 to 0.3 -0.3 to 0.6 -0.3 to 36 -0.3 to 0.3 2 V V V V V V V V V W V Unit
Symbol
Table 2.
Symbol RthJA TSTG TJ
Thermal data
Description Thermal Resistance Junction to ambient (mounted on demoboard) Storage temperature range Junction operating temperature range Value 45 -40 to 150 -10 to 125 Unit C/W C C
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PM6685
3 Block & pin connection diagrams
3
Figure 2.
Block & pin connection diagrams
Pin connection diagram (top view)
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3 Block & pin connection diagrams
PM6685
Table 3.
Pin No 1 2 3
Pin description
PM6685 SGND COMP3 FSEL Function Signal ground. Reference for internal logic circuitry. DC voltage error compensation pin for the 3.3V switching section. Frequency selection pin. It provides a selectable switching frequency, allowing either 200kHz/300kHz, 300kHz/400kHz or 400kHz/500kz operation of the 5V/ 3.3V switching sections. 3.3V SMPS enable input. The 3.3V section is enabled appling a high logic level (>2.4V) to this pin, while is disabled appling a low logic level (<0.8V). When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. If both EN3 and EN5 pins are low and SHDN pin is high the device enters in standby mode. Shutdown control input. The device enters its shutdown mode with 9A of supply current if VSHDN is less than the device off threshold voltage and doesn't restart until VSHDN is greater than the device on threshold voltage. The SHDN pin can be connected to Vbatt through a voltage divider to program an undervoltage lockout. In shutdown mode, the gate drivers of the two switching sections are in high impedance.
4
EN3
5
SHDN
6
Power Good ouput signal for the 3.3V linear regulator. This pin is an open drain PGOOD LDO3 output. It is shorted to GND if LDO3_SEL pin is at its low level or if the ouput voltage on LDO3 pin is lower than 2.6V. 3.3V Linear regulator output. LDO3 can provide 100mA peak current. If LDO3_SEL pin is connected to VREF and OUT3 is greater than the LDO3 bootstrap switch threshold, the LDO3 regulator shuts down and the LDO3 pin will be directly connected to OUT3 through a 3 (max) switch. If LDO3_SEL pin is at its low level the LDO3 is always OFF. If LDO3_SEL pin is at its high level the LDO3 is always ON. Output voltage sense for the 3.3V switching section.This pin must be directly connected to the output voltage of the switching section. Bootstrap capacitor connection for the switching 3.3V section. It supplies the highside gate driver. High-side gate driver ouput for the 3.3V section. Switch node connection and return path for the high side driver for the 3.3V section. Current sense input for the switching 3.3V section. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDSON sensing) or to the source of the synchronous rectifier (RSENSE sensing) to set the current limit threshold. Low-side gate driver output for the 3.3V section. Power ground. Low-side gate driver output for the 5V section. Signal ground for analog circuitry. Internal 5V regulator bypass connection. When the main 5V ouput voltage is greater than the boostrap switch threshold, the LDO5 regulator shuts down and the LDO5 pin will be directly connected to OUT5 through a 3 (max) switch. If not used, it must be tied to ground.
7
LDO3
8 9 10 11
OUT3 BOOT3 HGATE3 PHASE3
12
CSENSE3
13 14 15 16
LGATE3 PGND LGATE5 SGND2
17
V5SW
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PM6685
Table 3.
18 19
3 Block & pin connection diagrams
Pin description
LDO5 VIN 5V internal regulator output. LDO5 pin supplies all gate drivers, the internal circuitry and an external load. It can provide up to 100mA peak current. Device input supply voltage. A bypass filter (4 and 4.7 F) between the battery and this pin is recommended. Current sense input for the switching 5V section. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDSON sensing) or to the source of the synchronous rectifier (RSENSE sensing) to set the current limit threshold. Switch node connection and return path for the high side driver for the 5V section. High-side gate driver ouput for the 5V section. Bootstrap capacitor connection for the switching 5V section. It supplies the highside gate driver. Pulse skipping mode control input. It is a three states pin. If the pin is at its high level(e.g. cnnected to LDO5) the PWM mode is enabled. If the pin is at its low level (e.g. connected to GND), the pulse skip mode is enabled. If the pin is at its middle level (e.g. connected to Vref) the pulse skip mode is enabled but limiting the min frequency to 25KHz. 5V SMPS enable input. The 5V section is enabled appling a high logic level (>2.4V) to this pin, while is disabled appling a low logic level (<0.8V). When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high. If both EN3 and EN5 pins are low and SHDN pin is high the device enters in standby mode. Power Good ouput signal for the 5V section. This pin is an open drain ouput. The pin is pulled low if the output is disabled or is out of the specified window (approximately +/- 10% of its nominal value). Power Good ouput signal for the 3.3V section. This pin is an open drain ouput. The pin is pulled low if the output is disabled or is out of the specified window (approximately +/- 10% of its nominal value). Control pin for the 3.3V internal linear regulator. This pin determines three operative modes for the LDO3. If LDO3_SEL pin is at its low level the LDO3 is always OFF. If LDO3_SEL pin is at its high level the LDO3 is always ON If LDO3_SEL pin is connected to VREF and OUT3 is greater than the LDO3 bootstrap switch threshold, the LDO3 regulator shuts down and the LDO3 pin will be directly connected to OUT3 through a 3 (max) switch. Output voltage sense for the 5V switching section.This pin must be directly connected to the output voltage of the switching section. DC voltage error compensation pin for the 5V switching section. Device Supply Voltage pin. Connect this pin to LDO5 High accuracy output voltage reference (1.237V). It can deliver 50uA. Bypass to SGND with a 100nF capacitor.
20
CSENSE5
21 22 23
PHASE5 HGATE5 BOOT5
24
SKIP
25
EN5
26
PGOOD5
27
PGOOD3
28
LDP3SEL
29 30 31 32
OUT5 COMP5 VCC VREF
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4 Electrical characteristics
PM6685
4
Electrical characteristics
(VIN = 12V; Tamb = 0C to 85C unless otherwise specified)
Table 4.
Simbol VIN VCC
Supply section
Parameter Input voltage range IC supply voltage Turn-on voltage threshold Test Condition Vout=Vref, LDO5 in regulation Min. 6 4.5 4.8 4.6 4.75 50 5.5 V5SW >4.9V VOUT3 = 3.3V 1.8 1.8 12 3 3 25 Typ. Max. 28 5.5 4.9 Unit V V V V mV V
VV5SW
Turn-off voltage threshold Hysteresis
VV5SW RDS(on)
Maximum operating range LDO5 Internal Bootstrap Switch Resistance LDO3 Internal Bootstrap Switch Resistance
RDS(on)
OUT_ Discharge-Mode On-resistance OUT3, OUT5_ Discharge-Mode Synchronuos Rectifier Turn-on level 0.2 VOUT5>5.1V,VOUT3>3.34V V5SW to 5V LDO5, LDO3 no load SHDN connected to GND, ENx to GND, V5SW to GND
0.35
0.5
V
Pin
Operating Power consumption VIN Shutdown Current VIN Standby Current
4
mW A A
Ish Isb
14 150
18 250
Table 5.
Simbol VSHDN
Shutdown section
Parameter Device ON threshold Device OFF threshold Test Condition Min. 0.95 0.8 Typ. 1.35 0.85 Max. 1.6 0.9 Unit V V
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PM6685
Table 6.
Simbol
Electrical characteristics (continued)
Parameter Soft Start Ramp time Test Condition Min. 2 90 VCSENSE - VPGND VPGND - V PHASE VPGND - V PHASE OUT5=5V FSEL to GND OUT3=3.3V 917 1390 ns OUT3=3.3V OUT5=5V FSEL to LDO5 OUT3=3.3V 550 300 4.2V < VLDO5 < 5.5V -100A < IREF < 100A Falling edge of REF 250 mV -150 Both SMPS, 6V< V IN <28V 6V < V IN < 28V, 0 < ILDO5 < 50mA 6V < V IN < 28V, ILDO5 = 50mA LDO3_SEL tied to GND VLDO5 > UVLO, ILDO3 = 0A VOUT5 > 5.1V, V OUT3 > 3.34V 300 3.94 0 < ILDO3 < 50mA VLDO5 > UVLO HGATEx high state(pullup) HGATE driver on-resistance HGATEx low state (pulldown) LGATEx high state(pullup) LGATE driver on-resistance LGATEx low state (pulldown) 0.6 0.9 1.8 1.4 2.7 2.1 3.23 130 2.0 350 4 3.3 4.9 5.0 0.004 5.1 %/V V 1.224 -4 1.237 350 1.249 4 0.95 ns V mV V 688 1040 OUT5=5V ON-Time duration FSEL to VREF -5 -5 -120 2083 100 Typ. Max. 6 110 5 5 Unit ms A mV mV mV
ICSENSE
Input bias current limit Comparator offset Zero Crossing Comparatot Offset Fixed Negative current limit Threshold
TON
TOFFMIN
Minimum OFF-Time Voltage Accuracy
VREF
Load regulation Undervoltage Lockout fault threshold
COMP COMP
Over voltage clamp Under voltage clamp Line regulation LDO5 linear Output Voltage
VLDO5 LDO5 line regulation ILDO5 UVLO VLDO3 ILDO3
0.004
%/V
LDO5 Current limit Under Voltage Lockout of LDO5 LDO3 linear Ouput Voltage LDO3 Current limit
400 4.13 3.37 200 3
mA V V mA
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4 Electrical characteristics
PM6685
Table 6.
Simbol
Electrical characteristics (continued)
Parameter High side rise time High side fall time Low side rise time Test Condition HGATEx-PHASE from 1V to 4V CLOAD = 3.3nF LGATEx-PGND from 1V to 4V CLOAD = 8.2nF Both SMPS sections with respect to VREF. 113 66 107 90 VPGOOD3,5 forced to 5.5V ISink = 4mA 150 2.58 2.55 25 VPGOOD LDO3 forced to 5.5V ISink = 4mA 150 1 250 150 0.8 V SMPS enabled level Low level 2.4 0.5 1.0 VLDO5 -0.8 0.5 1.0 VLDO5 -0.8 0.5 1.0 VLDO5 -0.8 VLDO5 -1.5 V VLDO5 -1.5 V VLDO5 -1.5 V 116 70 110 92 Min. Typ. Max. 20 ns 20 40 ns 40 120 72 113 94 1 250 % % % % A mV V V mV A mV C Unit
OVP UVP PGOOD3,5
Over voltage threshold Under voltage threshold Upper threshold (VFB-VREF) Lower threshold (VFB-VREF)
IPGOOD3,5
PGOOD leakeage current
VPGOOD3,5 Ouput Low Voltage Rising voltage threshold PGOOD LDO3 IPGOOD_LD
O3
Falling voltage threshold Hytseresis PGOOD leakeage current Ouput Low Voltage Shutdown Temperature SMPS disabled level
VPGOOD_LD
O3
TSDN EN3,5
FSEL
Frequency selection range
Middle level High level Always-off level
3.3V Linear Regulator Selection LDO3 SEL Pin
Boostrap level Always-on level
Pulse Skip Mode SKIP PWM Mode Ultrasonic Mode
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PM6685
Table 6.
Simbol
4 Electrical characteristics
Electrical characteristics (continued)
Parameter Test Condition VEN3,4 = 0 to 5V VSKIP = 0 to 5V Min. Typ. Max. TBV TBV TBV TBV TBV A Unit
ILEAK
Input leakage current
VSHDN = 0 to 5V VFSEL= 0 to 5V VLDO3_SEL = 0 to 5V
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5 Functional & block diagram
PM6685
5
Figure 3.
Functional & block diagram
Block diagram
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PM6685
6 Package Mechanical Data
6
Package Mechanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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6 Package Mechanical Data
PM6685
Table 7.
Dim.
VFQFPN 5x5x1.0 32L Pitch 0.50
Databook (mm.) Min. Typ. 0.90 0.02 0.20 0.18 4.85 3.65 4.85 3.65 0.50 0.30 0.40 0.50 0.35 5.00 0.25 5.00 0.30 5.15 3.95 5.15 3.95 0.225 4.90 3.65 4.90 3.65 0.50 0.45 5.00 5.00 Max 1.00 0.05 Min. 0.80 0 0.25 0.275 5.10 3.95 5.10 3.95 Drawing (mm.) Typ. Max 1.00 0.05
A A1 A3 b D(3) D2(5) E(3) E2(5) e L
0.80 0
1. - VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. ___Very thin: A = 1.00mm Max. 2. - The leads size have been increased by Pb/Sn thickness in tin plating electrolytic process. 3. - Dimensions D & E do not include mold protusion, not to exceed 0,15mm. 4. - Package outline exclusive of metal burr dimensions. 5. - Dimensions D2 & E2 are not in accordance with JEDEC.
Figure 4.
Scheme Drawings
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PM6685
7 Revision history
7
Revision history
Date 23-Sep-2005 Revision 1 Initial release. Changes
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7 Revision history
PM6685
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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